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It turns out the Quartus is acting intelligent in this case. If you implement 4 or more instances using the same control signals, it packs the complete bit multiplexer in one LE. You can check with this top entity:
library ieee;
use ieee.std_logic_1164.all;
entity mux_5xN is
generic(
N: integer :=4
);
port(
clk : in std_logic;
reset : in std_logic;
sclr : in std_logic;
sload : in std_logic;
ena : in std_logic;
sel : in std_logic;
dia : in std_logic_vector(N-1 downto 0);
dib : in std_logic_vector(N-1 downto 0);
dic : in std_logic_vector(N-1 downto 0);
do : out std_logic_vector(N-1 downto 0)
);
end entity;
architecture rtl of mux_5xN is
component mux_5x1 is
port(
clk : in std_logic;
reset : in std_logic;
sclr : in std_logic;
sload : in std_logic;
ena : in std_logic;
sel : in std_logic;
dia : in std_logic;
dib : in std_logic;
dic : in std_logic;
do : out std_logic
);
end component;
begin
bits:
for i in 0 to N-1 generate
mux: mux_5x1
port map (
clk => clk,
reset => reset,
sclr => sclr,
sload => sload,
ena => ena,
sel => sel,
dia => dia(i),
dib => dib(i),
dic => dic(i),
do => do(i)
);
end generate;
end rtl;
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Hi FvM,
Thank you very much!
I tried your both examples, they worked as the presentation show. Also, for the second example, i try both your mux_5x1 and my mux_5x1, they are both ok!
Honored Contributor
