About multiplexer optimization issue need you help

Try this low-level primitive implementation:

library ieee;
use ieee.std_logic_1164.all;
entity mux_5x1 is
   port(
      clk    : in std_logic;
      reset  : in std_logic;
      sclr   : in std_logic;
      sload  : in std_logic;
      ena    : in std_logic;
      sel    : in std_logic;
      dia    : in std_logic;
      dib    : in std_logic;
      dic    : in std_logic;
      do     : out std_logic
   );
end entity;
architecture rtl of mux_5x1 is
signal d: std_logic;
component dffeas
    port (
        d : in std_logic;
        clk : in std_logic;
        ena : in std_logic;
        clrn : in std_logic;
        asdata : in std_logic;
        sclr : in std_logic;
        sload : in std_logic;
        q : out std_logic );
end component;
begin
d <= dib when sel = '1' else dia;
lc: dffeas 
port map (
   d => d,
   clk => clk,
   ena => ena,
   clrn => not reset,
   asdata => dic,
   sclr => sclr,
   sload => sload,
   q => do
);
end rtl;

The question is of course, why does the Quartus compiler to use this compact implementation? There are at least two possible answers:

- many of the signals connected to the DFFEAS primitive are LAB-wide signals, e.g. ena, sload, sclear. They can be only effectively used if more than one LEs is driven by the same signals.

- It's known that Quartus can't always find an optimal LE implementation, e.g. using the carry chain for non-arithmetical problems. Examples have been discussed at Altera forum before.