About edge aligned souce synchronous interface

Sort of. When driving a device and you've set up your clock constraints to be edge aligned, you need to decide which transfer works best for your external delays. If the external delays seem to have a "positive shift", such as a Tsu of 2.5 and Th of -1.5, which would become external delays of -max 2.5 and -min 1.5, then they have a "shift" of 2ns and it would make sense to put it into the default next edge. (8ns clock, 4ns data window). If the Tsu was -2.5 and Th of 1.5, which become external delays of -max -2.5 and -min -1.5, that is like a data shift of -2ns(with +/-0.5ns of skew) and hence a same edge transfer makes sense.

I believe there are other cases, such as when the FPGA is the receiver, and the transmitter might say it's data comes out with a skew of -2.5 to -1.5ns compared to the clock. Again, there is no phase-shift on the clock per se, but the data seems to be shifted.