About edge aligned souce synchronous interface

I won't disagree with your last statement.

One important point is that clock shifts and clock delays are very different. Clock delays are just physical delays that we all understand. Clock shifts define what the "ideal clock" looks like and affect the setup and hold relationships.

Let's say the FPGA is transmitting edge-aligned and the external device is not phase-shifting, so the setup relationship is 4ns and hold relationship is 0ns. Let's also say the external delays are 0 for now, just to keep it simple. Quartus II fitter tries to "solve" the setup and hold relationships by adding 2ns of delay to the output data path compared to the clock path. If it does this exactly, there will be 2ns of setup slack and 2ns of hold slack. (Of course it can't add exactly 2ns, due to PVT).

Now, if the user adds the multicycle 0 to get same-edge transfer, the setup relationship becomes 0ns and the hold relationship becomes -4ns. The way Quartus would solve this is by adding -2ns to the output data path compared to the output clock path. So they are very different things in this case.

I agree when we add in the external delays, it's possible to make one look like the other, but when looking at external datasheets, often one of these two scenarios fits perfectly, while the other one becomes a kluge of shuffling numbers around.