About edge aligned souce synchronous interface

Thanks Rysc for the detailed reply. I agree with all what you say but let me rephrase my question:

The equation for max output delay is this:

max delay = tSU + data delay - clk delay

and this equation applies if current launch is captured by next latch.

What I am raising is why not use same above equation for the case of edge aligned same edge capture since this scenario means somebody has to delay the clock.

In numbers and assuming your example of delaying clock by 90 degrees then max delay = tsu +data delay - 2 ns

e.g. = 1 + 0 - 2 = -1

TimeQuest does not want us to use the equation as such, instead it says add one UI (or set multicycle to 0); if we follow that we get:

max delay = 1 + 0 -2 + 4 = +3

Thus -1 & +3 mean to me the same in the sense of wrap-up. Why have they gone towards complicated two types of exceptions rather than using the one basic equation or adding it as third method. After all clock delay is clock delay whether it is by board or pll or any else.

edit: one final mystery. if clock and data is edge aligned at fpga then what is set output delay doing !!! aren't we lost in vague documentations??