Honored Contributor
Honored ContributorThe question raised by ertss is very reasonable and I don't think Rysc answered it. The question has two aspects; one is about concept of edge-aligned same edge capture and the other about how timing is controlled then... Rysc answered by passing timing responsibility to external device, yet the very subject is about how the fpga should be told to control timing (e.g. multicycle issue ...etc). I personally find this question very difficult to answer.
In fact, the most important clue is to know about the difference of these two cases(as documented by altera): edge aligned same edge capture and edge aligned opposite edge capture. What then decides which is which. It could be explained as follows: The default setup relationship is between current launch edge and next latch edge and the delay equations apply then directly. If however it is same edge capture then first what is this same edge capture? It could occur if clock is delayed such that the current edge indeed physically captures instead of next edge in the external device. In this case I wonder what will we get if we apply delay equation : delay = tSU + data delay -clock delay so if say tSU = 1ns, data delay = 0, clk delay = 4 ns then delay = 1 + 0 - 4 = -3ns I wonder is altera saying don't use minus but add multicycle of 0 or one clk period instead !!! In particular I note that altera in this context does not use the terms lauch/latch clocks but data clock/output clock which implies edge aligned at fpga but not at latch of external device. We certainly need Altera to help us understand their concepts.
