Forum Discussion
Yamada1
Occasional Contributor
Occasional ContributorAbout "delayed addition" in fitter report
I am designing a design that takes in ADC data and performs signal processing, but due to the mismatch in PN placement on the ADC side and FPGA side and the need to make equal length wiring on the bo...
By default, the Fitter intentionally adds additional routing delay where needed to help meet hold timing requirements. You can disable this globally in the optimization settings (I forget where and don't have Quartus open at the moment) or I think there is an assignment you can use in the Assignment Editor to specify where you want this done (or not).
RichardT_altera
Super Contributor
Super ContributorThank you for acknowledge the solution provided.
To add-on, the setting that Strell mentioned is called "Optimize Hold Timing". (Project>Setting> Compiler Setting > Advanced Fitter Setting)
As your question has been addressed, I now transition this thread to community support.
Thank you.
Best Regards,
Richard Tan
