Forum Discussion
Yamada1
Occasional Contributor
Occasional ContributorAbout Clock Constraints
I want to apply a timing constraint, but when I create an SDC file and try to specify it with create clock or click the List button on the Name Finder, I get the error "Error: In order to edit SDC co...
You can just compile to have the timing netlist during (post map/post fit). In Timing Analysis, there should be able to detect the clock you specify in sdc. Also I suggest you to migrate to latest Quartus for better usability and there lot of bug/fix.
Yamada1Occasional Contributor
Occasional ContributorThank you for answering.
The Quartus I am using is the Standard Edition.
The device used is Arria10 GX, and the version of Quartus is 18.1.1. For the time being, we will proceed with the design after the fitter is completed.
I apologize for the inconvenience, but it would be helpful if you could teach me.
sstrell
Super Contributor
Super ContributorNot sure what you want to learn. There is plenty of documentation and training available. Start here: https://learning.intel.com/developer/learn/course/external/view/elearning/839/intelr-quartusr-prime-pro-software-timing-analysis-part-1-timing-analyzer
