Forum Discussion
Occasional ContributorAbout Clock Constraints
You can just compile to have the timing netlist during (post map/post fit). In Timing Analysis, there should be able to detect the clock you specify in sdc. Also I suggest you to migrate to latest Quartus for better usability and there lot of bug/fix.
Occasional ContributorThank you for answering.
I understand that even if Start Compilation is completed up to Timing Analysis, a timing netlist will not be created.
I also checked here, but is the following procedure correct for creating a timing netlist?
1) Start Timing Analyzer
2) Netlist → Create Timing Netlist on the Timing Analyzer
At the stage up to synthesis, the above procedure will also fail with a message telling you to complete the fitting.
It would be helpful if you could also teach us the procedure for creating a timing netlist at the stage of completing synthesis.
I apologize for the inconvenience, but it would be helpful if you could teach me.
sstrellSuper Contributor
Are you using Standard (Lite) or Pro? If Pro, you have to have completed at least the Plan stage of the Fitter. In Standard you can create a post-synthesis timing netlist. This is not available in Pro.
