Forum Discussion
Yamada1
Occasional Contributor
Occasional ContributorAbout Clock Constraints
I want to apply a timing constraint, but when I create an SDC file and try to specify it with create clock or click the List button on the Name Finder, I get the error "Error: In order to edit SDC co...
You can just compile to have the timing netlist during (post map/post fit). In Timing Analysis, there should be able to detect the clock you specify in sdc. Also I suggest you to migrate to latest Quartus for better usability and there lot of bug/fix.
sstrell
Super Contributor
Super ContributorAs the error states, you have to create a timing netlist to use those features. This is separate from compiling the design. The timing netlist is based on completed stages of compilation, either synthesis or fitting. It's a database of timing information based on a stage of compilation and is required for working with the tool.
