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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

About Clock Constraints

I want to apply a timing constraint, but when I create an SDC file and try to specify it with create clock or click the List button on the Name Finder, I get the error "Error: In order to edit SDC co...
  • IntelSupport's avatar
    IntelSupport
    3 years ago

    You can just compile to have the timing netlist during (post map/post fit). In Timing Analysis, there should be able to detect the clock you specify in sdc. Also I suggest you to migrate to latest Quartus for better usability and there lot of bug/fix.


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

As the error states, you have to create a timing netlist to use those features. This is separate from compiling the design. The timing netlist is based on completed stages of compilation, either synthesis or fitting. It's a database of timing information based on a stage of compilation and is required for working with the tool.