about chip planner in Quartus II

Generally, the FPGA architecture is optimzed for fast synchronous procssing. For this reason, capturing of data with an edgle triggered FF is probably better defined and at least more precisely predicted by the Quartus timing analysis. But in this case a chain of latches controlled by a common enable signal seems to be more suitable. It can be used to freeze the signal propagating through the delay chain and capture it e. g. to a serial shift register for readout.