about chip planner in Quartus II

I don't think that we need to argue about a 6 to 7 ns difference. The actual pin-to-pin delay depends on the selected I/O cells and much more. I just wanted to mention, that 7 ns would be a typical pin-to-pin delay for a MAX II short logic path involving a single LE. Your Chip Planner results basically seem to confirm this value.

You can get a slower response with modified I/O parameters like lower current strength or slow slew-rate, or with excessive capacitive load of the output.

As far as I understand your application, the output delay part of pin-to-pin delay doesn't matter anyway. So, if you doubt the timing simulation or Chip Planner results, you have to perform differential timing measurements with signal capture inside the device. It may be meaningful, to use a basic TDC design (if you already have one) for test.

As another supplement to my previous posting. The said uniform delay spacing can't be seen, when routing the signals to output pins, cause arbitray routing delays are added in this case. But this isnt't a model for TDC operation, I think.

I also wonder about a suitable basic structure for the TDC design. I suppose, it may be a chain of asynchronous latches, that can be used as delay and storage element in-one. Usage of synchronous FF would imply different LEs for delay and storage and thus involve additional routing delays and delay variation, and require a doubled LE amount.