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Altera_Forum's avatar
Altera_Forum
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17 years ago

about chip planner in Quartus II

I tried to change the placement and routing by Chip planner, and estimate the delay time. For example, I input a signal to a buffer and then output, the delay time in Chip planner is: after I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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OK,

I assume that your paths are asynchronous. Is it possible that you post some of your Listed paths ? In case of the claasic timing analyzer you find them under tpd.

Kind regards

GPK

--- Quote End ---

Hi, pletz.

I took some pictures of my test file, including schematic plot, tpd data, the chipplanner and waveform.

Maybe it will be more clear about my question that

the delay time estimated is 6.34 ns, not as same as 15 ns of the wavefrom.

Thanks.