about chip planner in Quartus II

I wanted to supplement my previous remark regarding the reported pin-to-pin delay of 15 ns. For a pin driven by a short asynchronous logic path (through a single LE), I observe about 5 ns pin-to-pin delay with Cyclone II or III and 3.3V LVTTL IO standard. This delay is also indicated by Quartus timing simulation, and as I suppose by all other tools, that are using the same device data base, e. g. Pin Planner and Timing Analysator.

With MAX II, that is utilized by ccmkn, the basic pin-to-pin delay i slightly larger, about 7 ns, but far away from said 15 ns. Also the micro-timing parameters from MAX II datasheet are basically resulting in a similar delay amount.

When designing delay chains with cascaded LEs, you observe a rather uniform delay spacing around 0.5 ns within a single LAB. Advancing to the next LAB, larger steps of e.g. 1.5 ns can be seen. So the basic problem with the said TDC problem is the design of uniform delay chains across LAB boundaries, I think. Besides explicite assignment of LEs, it requires most likely partially parallel structures to get sufficient resolution during LAB boundary crossing.