--- Quote Start ---
Hi, pletz.
The main problem is that the delay time which I measured with the scope is not as same as I simulated in Chip planner. The resolution I want to have is at least 0.5 ns, but of course, it is better to have better resolution if possible.
In my design, I am not measure the length of the pulse. Instead, I want measure the delay time of two pulses (That is what TDC does). And I have to measure the delay time of buffers and latches first. That is why I do this test.
By the way,
Beside the delay times shown in chip planner, and the pin transition time of gee just tought me. Is it possible there are additioal delays that I didnt figure out?
--- Quote End ---
Is the listed path in Gee's attachment one of yours paths ?
If yes, you have a delay of 17.211 ns. The delay is could be splitted into 5.063ns for cell delay ( in the listing all value for "CELL") and 12.148ns for interconnect delay ( in the listing all values for "IC")
Honored Contributor
