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Altera_Forum
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17 years ago

about chip planner in Quartus II

I tried to change the placement and routing by Chip planner, and estimate the delay time. For example, I input a signal to a buffer and then output, the delay time in Chip planner is: after I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi, pletz.

The main problem is that the delay time which I measured with the scope is not as same as I simulated in Chip planner. The resolution I want to have is at least 0.5 ns, but of course, it is better to have better resolution if possible.

In my design, I am not measure the length of the pulse. Instead, I want measure the delay time of two pulses (That is what TDC does). And I have to measure the delay time of buffers and latches first. That is why I do this test.

By the way,

Beside the delay times shown in chip planner, and the pin transition time of gee just tought me. Is it possible there are additioal delays that I didnt figure out?