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Altera_Forum's avatar
Altera_Forum
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17 years ago

about chip planner in Quartus II

I tried to change the placement and routing by Chip planner, and estimate the delay time. For example, I input a signal to a buffer and then output, the delay time in Chip planner is: after I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I worked with CPLD, MAX II: EPM570T100C5.

And here is my testing:

I used function generator to generate 3.3 V square wave as input to CPLD (here has a T-connector to have the input into scope),

and CPLD output to the scope to have the waveform.

Is my measurement wrong to have the 15 ns not as my expect delaytime?