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Altera_Forum's avatar
Altera_Forum
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17 years ago

about chip planner in Quartus II

I tried to change the placement and routing by Chip planner, and estimate the delay time. For example, I input a signal to a buffer and then output, the delay time in Chip planner is: after I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You didn't tell, which device you have been using in your test, but neither the delay nor the rise-times (also of the output signal) are in a range I'm used to with recent Altera devices.

P.S.: You may be able to achieve it using minimum current strength and a high capacitive load, but then you aren't measuring device delays.