about chip planner in Quartus II

Some general remarks. Most FPGA tools are mainly designed to synthesize synchronous logic. They have limited capabilities in asynchronous logic synthesis.

I understand, that you intend a delay chain with uniform stage-to-stage delay. The feasibility may depend on the number of stages. You can expect almost equal delays within a logic array block, but surely get additional delays when routing through LAB interconnects.

So, even with completely manual placement of logic elements by location assignments, it may be difficult to achieve the intended timing.

Finally, I reviewed the waveform you posted at start of the thread. With this kind of slow rising signals, it's effectively impossible to decide about any real device delay. The said 15 ns should be expected a measurement artefact rather than a real value. Delta delays determined at the digital side may be valid anyway.