A synchronous clear enable conter RTL

I have issues with RTL of simple counter: a synchronous clear enable counter.

I use Altera template to be confident as much as possible.

http://quartushelp.altera.com/14.1/mergedprojects/hdl/vlog/vlog_pro_counters.htm

https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-handbook.pdf HDL guides for counters on 12-57

I expect such counter to consist of one adder, one mux and one register, but I get two muxes if using provided template. Instead of using EN input of register second mux is implemented. How do I specify to use EN input of register?

Can someone provide information on this issue? Maybe I don't understand something.

I've tried to change synthesis options and it did't work.

I can implement my vision of RLT with one MUX using d = a?b:c operand. But I find it kind of akward.

See code below.

module counter 
(
input en, clk, rst,
output reg  count,
output reg  count2);
// One MUX RTL
wire  new_count = rst ? 4'd0 : count + 1;
always @(posedge clk) begin
 if (en) count <= new_count;
end
// Two MUX RTL (using altera template)
always @(posedge clk) begin
if (rst) count2 <= 0;
else if (en) count2 <= count2 + 1;
end
endmodule