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Altera_Forum's avatar
Altera_Forum
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15 years ago

A noob in need!!!

Hi all,

I just want to say that I am pretty much a complete noob with regards to Quartus II, VHDL and FPGAs in general so please bear with me, and any help or guidance is very much appreciated.

I am using the Quartus II 10.0 sp1 web edition software along with a .rbf loader to load the compiled programs onto the chip. I am using the MORPH-IC-II board from FTDI which has a cyclone II ESP2C5F256C8 and an FTDI FT2232HQ chip.

I have been tasked with programming an FPGA to take a 24 bit input and a clock line, basically put this into a massive FIFO then send the data using over USB using the FTDI chip.

I think the easiest way to do this will be to use an 8bit and very deep fifo, and a demultiplexor to put the data into the fifo.

But as I said I am a complete noob, to all of this so am taking baby steps!

The first thing that I have been trying to do is get the FT245 style interface working between the FT2232 chip and the Cyclone II.

At the moment I am trying to echo a character back to hyperterminal that is sent to the dev board over USB and I have been struggling even with this. I have tried using bidir pins for my 8 data channels in the FT2232 to Cyclone II interface with an ALT_IOBUF connected to it, going to a DFF and back to the output part of the ALT_IOBUF. My problem is probably within my control logic, but also I have been struggling to find out wether the OE pin of the ALT_IOBUF is active high or active low. i.e. whether putting a 0 in makes it an output or an input. I have been assuming it is active low so far.

Any hints, tips, help or even links to useful tutorials or threads is much appreciated. Apologies if I don't appear to have researched too much but as time is tight I need to learn fast and can't afford to troll through forums for days just to get a little progress.

Thanks in advance for any and all help!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi all,

    I am still stuck with this FPGA board not working as expected.

    I have worked out some of my initial problems and now have the FT2232 chip configured properly, so that the two channels are configured as 245FIFO in hardware by changing the settings in the EEPROM, and written a small application in C# to set the operation mode of the FT2232 to Synchronous 245 FIFO <-- and I know this part works as I can now see the 60MHz clock when I proble the clock line.

    However I still can't send characters over USB and have them echo'd back to my PC. I don't know whether my control logic is incorrect, whether its just because I don't know how to use Quartus II properly or something else is wrong.

    So far I have primarily been using the Quartus II Block Diagram/Schematic File to produce my design.

    I have 8 bidirectional pins, connected to 8 ALT_IOBUF buffers. The oe for the buffers (which is different to the OP_EN pin which goes to the output enable on the FT2232 chip) should go low when I want to write/output to the FT2232 USB chip. IS THIS CORRECT? As I couldn't find where it says whether this should be high or low to cause the bidirectional pin to act as an output. I know that there is tri-state logic involed, but as far as I can tell that just means that when the output is not enabled the pin has Hi-Z??

    The ALT_IOBUF buffers are then just connected into 8 d-flip flops the outputs of which are connected back to the output buffer side of the ALT_IOBUF buffers.

    At the moment all I wish to do is to read any characters recieved by the USB chip into the FPGA, then load them back into the FT2232 transmit FIFO to be echo'd back to the host PC and I am struggling. Any help, idea's, examples or just things to lookup would be appreciated as at the moment I am trying and failing!

    The application note for the FT2232 chip can be found here:

    ftdichip.com/Support/Documents/AppNotes/AN_130_FT2232H_Used_In_FT245%20Synchronous%20FIFO%20Mode.pdf

    Regards,

    Lee