Honored Contributor
Honored ContributorHi all,
I am still stuck with this FPGA board not working as expected. I have worked out some of my initial problems and now have the FT2232 chip configured properly, so that the two channels are configured as 245FIFO in hardware by changing the settings in the EEPROM, and written a small application in C# to set the operation mode of the FT2232 to Synchronous 245 FIFO <-- and I know this part works as I can now see the 60MHz clock when I proble the clock line. However I still can't send characters over USB and have them echo'd back to my PC. I don't know whether my control logic is incorrect, whether its just because I don't know how to use Quartus II properly or something else is wrong. So far I have primarily been using the Quartus II Block Diagram/Schematic File to produce my design. I have 8 bidirectional pins, connected to 8 ALT_IOBUF buffers. The oe for the buffers (which is different to the OP_EN pin which goes to the output enable on the FT2232 chip) should go low when I want to write/output to the FT2232 USB chip. IS THIS CORRECT? As I couldn't find where it says whether this should be high or low to cause the bidirectional pin to act as an output. I know that there is tri-state logic involed, but as far as I can tell that just means that when the output is not enabled the pin has Hi-Z?? The ALT_IOBUF buffers are then just connected into 8 d-flip flops the outputs of which are connected back to the output buffer side of the ALT_IOBUF buffers. At the moment all I wish to do is to read any characters recieved by the USB chip into the FPGA, then load them back into the FT2232 transmit FIFO to be echo'd back to the host PC and I am struggling. Any help, idea's, examples or just things to lookup would be appreciated as at the moment I am trying and failing! The application note for the FT2232 chip can be found here: ftdichip.com/Support/Documents/AppNotes/AN_130_FT2232H_Used_In_FT245%20Synchronous%20FIFO%20Mode.pdf Regards, Lee
