--- Quote Start ---
The code is multiplying same data?? by all coeffs then summing up products. I don't know what this means in DSP sense.
--- Quote End ---
It doesn't seem to make sense in VHDL sense. Each CQRealReg(I) is assigned twice per clock cycle, so the first assignment is discarded. It seems like the design output doesn't depend on the input and all logic will be removed during synthesis.
The code is using VHDL signals as if they where variables.
Update:
I overlooked that C
qRealReg and C
sRealReg are different signals. So the code is probably correct. But hard to read nevertheless. As previously mentioned by others, there are better ways to write sign extension etc. in VHDL.
Honored Contributor
