Forum Discussion
hans86
New Contributor
6 years agoHi Alan,
I just tried it out and it works fine for me (Modelsim DE 2019.2). I have a simple counter in VHDL defined as:
signal count_s : std_logic_vector(7 downto 0);
process (reset, clk)
begin
if reset='1' then
count_s <= (others => '0');
elsif rising_edge(clk) then
count_s + '1';
end if ;
end process;During simulation I can force it to any value and it continues from the forced value:
force -deposit test_tb/u1/count_s 36
Is your counter a variable? In that case you need to use the change command.
Regards,
Hans.