Occasional ContributorHey guys,
I am doing a project and I found out that this comment caused a compilation error! I just don't know why
comment : /*/\/\/\/\/\/\/\/\/\/\*/
could anyone please tell me why ?
Super ContributorWhat does the error say? Perhaps the first * is being interpreted as the start and end of the comment.
#iwork4intel
Occasional Contributorit says:
"Object(the name of the signal) is not declared, Verify the object name is correct. If the name is correct, declare the object."
for all regs and wires inside the Verilog code
Regular ContributorHi,
Could you please check with Verilog-2001 version? older version of verilog might not supported.
'Assignments' Menu-> 'Settings'.
Regards,
Vicky
Occasional ContributorYes it is Verilog 2001, I think this happened because of the escaping mechanism in Verilog (\ " ")
