Forum Discussion
AAlas3
Occasional Contributor
6 years agoit says:
"Object(the name of the signal) is not declared, Verify the object name is correct. If the name is correct, declare the object."
for all regs and wires inside the Verilog code
it says:
"Object(the name of the signal) is not declared, Verify the object name is correct. If the name is correct, declare the object."
for all regs and wires inside the Verilog code