Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

8b10b serdes questions

Hello world!

I am trying to make a serial link, 400 Mbps in two Cyclones III, 2 channels, 5 serialisation factor (the output of one 8b10b encoder). Though everything seems within specs, there are a number of reasons why I might lose my deadline:

1. Cyclone III does not support Dynamic bit aligment, so I made a loop with the idle 10b word (K28.5). While it is being sent and byte out is not 8'b101_11100 as it should, the data_alignment of the deserialiser pulses. In theory. In practice, the error bit is asserted so no byte out. Any ideas?

2. Since this link will most likely have random physical length, I guess I should make some phase allignment as well. I use an external pll for the deserialiser, on which I want to use the phase alignment possibilty of the megacore. Still, I don't find somewhere any guidelines as to where and how should I connect it, and what kind of loops should I write. There might be sth, could somebody direct me there?

That it is more or less, I would be really happy if you could help me, I think that what I ask is pretty much corebook, so I guess it will be helpful for a lot of people as well.

Thank a lot in advance

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    One way is to use the 10b words to align the deserializer, not the decoder output.

    If you know you never transmit a K28.7 then you known whenever your deserializer has 10'b0011111xxx" or a 10'b1100000xxx" it has a properly aligned word.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hello everybody,

    I think it would be useful not to leave "dangling" posts, so I will present what I didn't in the end:

    Checking the word before decoding was indeed a good hint, so while the word was not acceptable, bit shifting using the "data_align" port of the ALTLVDS_RX megacore and phase shifting using the ports as presented in page 5-32 of the cyclone iii handbook, using external pll.

    ALWAYS REMEMBER: Fast clock should be half the frequency of the bit rate sent.

    Thanks a lot, looking forward to next almost lost deadline :P