Forum Discussion
New Contributor3-Wire SPI IP Component with Arria 10
Hi,
Check this link https://www.intel.com/content/www/us/en/docs/programmable/683113/21-3-19-2-0/generating-the-design.html
At Example Design tab, Select Design and enable Generate 3-wire SPI module then Generate Example Design. You should see 3-wire SPI module spi_3wire.v being generated.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.
New ContributorHi,
Thank you very much for your insight. I could manage to generate the 3-wire SPI module. However I find myself stucked when compiling, after having added the 3-wire SPI either in my top.sv or directly in the qsys design. I included the necessary files in the project navigator, and I get the following error during Analysis & Synthesis stage :
Illegal connection found on I/O output buffer primitive u0|myspi_3wire_0|myspi_3wire_0|u_sdio|gpio_0|core|i_loop[0].altera_gpio_bit_i|output_buffer.obuf to u0|myspi_3wire_0|myspi_3wire_0|u_sdio|gpio_0|core|i_loop[0].altera_gpio_bit_i|input_buffer.ibuf. The IO output buffer should only drive out to a top-level pin.
This comes from the "alteria_gpio.sv file. I believe this may just be because I added in a wrong way the 3-wire SPI IP generated from ed ?
Regards
