2D Array VHDL

This is the problem of defining new arrays of std_logic, especially 2D arrays of std_logic. (Thanks altera!). Just to note, your data type is NOT a 2D array, its a 1D array of a 1D array type.

Like the error says, you cannot part slice into 2d arrays. You can only access individual elements or the entire array.

There is only one way for you to work around this error: assign each bit individually.

The hand coded way will be long an tedious:

data(0,0) <= my_data(0)(0);

data(0,1) <= my_data(0)(1);

--etc

--zzzzzzzzzz

but to make your life simpler, why not simply write a conversion function?

function convert_normal_to_stupid_type(s : t_32bit_data_array) return altera_mf_logic_2D is
  variable ret : altera_mf_logic_2D(s'range, 31 downto 0);
begin
  for i in s'range loop
    for j in 31 downto 0 loop
      ret(,i,j) <= s(i)(j);
    end loop;
  end loop;
  return ret;
end function;
....
data <= convert_normal_to_stupid_type(my_data);