Forum Discussion

alexislms's avatar
alexislms
Icon for Contributor rankContributor
4 years ago
Solved

22.1 PRO: (*preserve_for_debug*) signals not preserved

1. I follow the steps "2.4.1. Preserving Signals for Monitoring and Debugging" in 683819 2. I watched and followed this Intel-FPGA video: https://www.youtube.com/watch?v=sEKc2ut42gU ...
  • Nurina's avatar
    Nurina
    4 years ago

    Hello,


    Alright thanks for the feedback. I've let them know that you expect this fix to apply to all data types.

    In the meantime your only workaround is to have the signal connected to an i/o port.

    With that, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    Regards,

    Nurina


    P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution.


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

Again, preserve for debug is not for I/O. It's for internal nodes.

You can use noprune or virtual pins. I like virtual pins because I don't need to make any changes to the HDL code, just create an assignment, just like using preserve for debug as an assignment instead of an attribute.

alexislms's avatar
alexislms
Icon for Contributor rankContributor
4 years ago

Sorry for the misunderstanding, what do you call I/O? Actual I/O of the fpga (ports of the top connected to pins) or any instance ports?

Here is the code showing the signal I'd like to debug and that isn't kept by Quartus:

module top(
  ...
);

(*preserve_for_debug*)logic sigtodebug; //not used, just want to see it in Signaltap

mymod mymod_inst (
  .out_a (sigtodebug),
  .in_b ('0),
  .in_c ('0)
);

endmodule