"21'b0" Verilog to VHDL explination please

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Now I have in VHDL:

cont <= "000000000000000000000";

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It's O.K. if you love it long-winded.

You'll notice, that in Verilog also

cont <= 0;

is accepted as legal code, but giving a warning about assigning a 32 bit value to a 21 bit signal or something like that.

In VHDL, the assigned constant must have the correct bit length if not using special constructs like OTHERS =>.