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Altera_Forum's avatar
Altera_Forum
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14 years ago

"21'b0" Verilog to VHDL explination please

Hello In Verilog I got this code: cont <= 21'b0; oRST <= 1'b1; What does it mean in VHDL?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks!

Now I have in VHDL:

cont <= "000000000000000000000";

oRST <= '1';

:)