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Altera_Forum's avatar
Altera_Forum
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16 years ago

2 memory instances with different usages.

Hi,

I have a MegaWizard created memory component in Quartus II 9.1 -

24 bit x 4k Word x 3 port

I have two different instances of this component, which should both be embedded in identical circuitry.

One instance has 3 x the resource usage of the other : 196608 vs. 65536

I could understand this if one instance usage was different to the other and was being optimised away, but this should be a symmetric design.

Any ideas ?

cheers,

Beau

;|mem_24b_4k_3p:inst15| ; 0 (0) ; 0 ; 65536 ; 0

; |alt3pram:alt3pram_component| ; 0 (0) ; 0 ; 65536 ; 0

; |altdpram:altdpram_component1| ; 0 (0) ; 0 ; 32768 ; 0

; |altsyncram:ram_block| ; 0 (0) ; 0 ; 32768 ; 0

; |altsyncram_g4q1:auto_generated| ; 0 (0) ; 0 ; 32768 ; 0

; |altdpram:altdpram_component2| ; 0 (0) ; 0 ; 32768 ; 0

; |altsyncram:ram_block| ; 0 (0) ; 0 ; 32768 ; 0

; |altsyncram_g4q1:auto_generated| ; 0 (0) ; 0 ; 32768 ; 0

;|mem_24b_4k_3p:inst6| ; 0 (0) ; 0 ; 196608 ; 0

; |alt3pram:alt3pram_component| ; 0 (0) ; 0 ; 196608 ; 0

; |altdpram:altdpram_component1| ; 0 (0) ; 0 ; 98304 ; 0

; |altsyncram:ram_block| ; 0 (0) ; 0 ; 98304 ; 0

; |altsyncram_g4q1:auto_generated| ; 0 (0) ; 0 ; 98304 ; 0

; |altdpram:altdpram_component2| ; 0 (0) ; 0 ; 98304 ; 0

; |altsyncram:ram_block| ; 0 (0) ; 0 ; 98304 ; 0

; |altsyncram_g4q1:auto_generated| ; 0 (0) ; 0 ; 98304 ; 0

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hi,

    I have a MegaWizard created memory component in Quartus II 9.1 -

    24 bit x 4k Word x 3 port

    I have two different instances of this component, which should both be embedded in identical circuitry.

    One instance has 3 x the resource usage of the other : 196608 vs. 65536

    I could understand this if one instance usage was different to the other and was being optimised away, but this should be a symmetric design.

    Any ideas ?

    cheers,

    Beau

    ;|mem_24b_4k_3p:inst15| ; 0 (0) ; 0 ; 65536 ; 0

    ; |alt3pram:alt3pram_component| ; 0 (0) ; 0 ; 65536 ; 0

    ; |altdpram:altdpram_component1| ; 0 (0) ; 0 ; 32768 ; 0

    ; |altsyncram:ram_block| ; 0 (0) ; 0 ; 32768 ; 0

    ; |altsyncram_g4q1:auto_generated| ; 0 (0) ; 0 ; 32768 ; 0

    ; |altdpram:altdpram_component2| ; 0 (0) ; 0 ; 32768 ; 0

    ; |altsyncram:ram_block| ; 0 (0) ; 0 ; 32768 ; 0

    ; |altsyncram_g4q1:auto_generated| ; 0 (0) ; 0 ; 32768 ; 0

    ;|mem_24b_4k_3p:inst6| ; 0 (0) ; 0 ; 196608 ; 0

    ; |alt3pram:alt3pram_component| ; 0 (0) ; 0 ; 196608 ; 0

    ; |altdpram:altdpram_component1| ; 0 (0) ; 0 ; 98304 ; 0

    ; |altsyncram:ram_block| ; 0 (0) ; 0 ; 98304 ; 0

    ; |altsyncram_g4q1:auto_generated| ; 0 (0) ; 0 ; 98304 ; 0

    ; |altdpram:altdpram_component2| ; 0 (0) ; 0 ; 98304 ; 0

    ; |altsyncram:ram_block| ; 0 (0) ; 0 ; 98304 ; 0

    ; |altsyncram_g4q1:auto_generated| ; 0 (0) ; 0 ; 98304 ; 0

    --- Quote End ---

    Hi,

    without knowing the design details it is difficult to say, but I would look to the modules in front and behind the memory. I would expect that the synthesis tool could optimize the

    two memories different.

    Kind regards

    GPK