2 bit carry ripple carry adder delay problem

I am working on 2 bit carry using component FA .Each gate has delay 2nsec.Expected delays for carry out =8nsec,so =2 nsec ,s1=6 nsec.but i am getting s0=2nsec,s1=6nsec and carry=4nsec. The code and test bench waveform is with attachment.I am using xilinx 9.1i