10G Example design simulation tcl error

Hi everyone,

I am new to the Altera/Intel framework and maybe some of the questions I am going to ask are really dumb. I am still getting used to the new interface and I don't know where all the options are.

I am trying to create the 10G Example design based on the Low Latency Ethernet 10G MAC IP. The project creation and Analysis & Synthesis work as expected but when I try to simulate the design I am facing some problems with the tool.

As stated in the [intel arria 10 low latency ethernet 10g mac design example user guide (https://www.altera.com/documentation/nfa1438753448747.html)], to simulate the design at the command prompt I go to the simulation folder and run the following command.

vsim -c -do tb_run.tcl

I see the following output of the terminal

# Top level modules:#      altera_eth_10g_mac_base_r#  End time: 13:50:11 on Nov 07,2017, Elapsed time: 0:00:00#  Errors: 0, Warnings: 0#  Start time: 13:50:11 on Nov 07,2017#  vlog ./../../../rtl/altera_eth_10g_mac_base_r_wrap.v #  Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016#  -- Compiling module altera_eth_10g_mac_base_r_wrap#  

... a lot more of the same, and at the end ...

#  Top level modules:#      altera_eth_10g_mac_base_r_wrap#  End time: 13:50:11 on Nov 07,2017, Elapsed time: 0:00:00#  Errors: 0, Warnings: 0#  Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016#  Start time: 13:50:11 on Nov 07,2017#  vlog -sv ./../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv -work altera_common_sv_packages #  -- Compiling package altera_xcvr_native_a10_functions_h#  #  Top level modules:#      --none--#  End time: 13:50:11 on Nov 07,2017, Elapsed time: 0:00:00#  Errors: 0, Warnings: 0#  Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016#  Start time: 13:50:11 on Nov 07,2017#  vlog -sv ./../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv -L altera_common_sv_packages -work altera_eth_10gbaser_phy_altera_xcvr_native_a10_170 #  -- Compiling module alt_xcvr_resync#  ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_resync" is being recompiled as unprotected.#  ** Fatal: Unexpected signal: 11.#  ** Error: ./../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv(97): Verilog Compiler exiting#  End time: 13:50:12 on Nov 07,2017, Elapsed time: 0:00:01#  Errors: 2, Warnings: 1#  ** Error: /home/pablo/intelFPGA/17.0/modelsim_ase/linuxaloem/vlog failed.#  Error in macro ./tb_run.tcl line 38#  /home/pablo/intelFPGA/17.0/modelsim_ase/linuxaloem/vlog failed.#      while executing#  "vlog -sv ./../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv -L altera_common_sv_packages -work altera_eth_10..."#      ("eval" body line 1)#      invoked from within#  "eval  vlog -sv $USER_DEFINED_COMPILE_OPTIONS                                     "$QSYS_SIMDIR/../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_na..."#      ("eval" body line 37)#      invoked from within#  "com"

As I am using the unmodified generated reference design so I wasn't expecting to face this kind of problems with the simulation.

The error appears to be in this file:

Error: ./../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv(97): Verilog Compiler exiting

The content of the file is the following code. The line where the error is pointed is the last endmodule of the code.

`timescale 1ps/1ps 
module alt_xcvr_resync# (
    parameter SYNC_CHAIN_LENGTH = 2,  // Number of flip-flops for retiming. Must be >1
    parameter WIDTH             = 1,  // Number of bits to resync
    parameter SLOW_CLOCK        = 0,  // See description above
    parameter INIT_VALUE        = 0
  ) (
  input   wire              clk,
  input   wire              reset,
  input   wire   d,
  output  wire   q
  );
localparam  INT_LEN       = (SYNC_CHAIN_LENGTH > 1) ? SYNC_CHAIN_LENGTH : 2;
localparam   L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
  for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
    wire                d_in;   // Input to sychronization chain.
    (* altera_attribute  = "disable_da_rule=D103" *)
    reg    sync_r = L_INIT_VALUE;
    assign  q   = sync_r; // Output signal
    always @(posedge clk or posedge reset)
      if(reset)
        sync_r  <= L_INIT_VALUE;
      else
        sync_r  <= {sync_r,d_in};
    // Generate asynchronous capture circuit if specified.
    if(SLOW_CLOCK == 0) begin
      assign  d_in = d;
    end else begin
      wire  d_clk;
      reg   d_r = L_INIT_VALUE;
      wire  clr_n;
      assign  d_clk = d;
      assign  d_in  = d_r;
      assign  clr_n = ~q | d_clk; // Clear when output is logic 1 and input is logic 0
      // Asynchronously latch the input signal.
      always @(posedge d_clk or negedge clr_n)
        if(!clr_n)      d_r <= 1'b0;
        else if(d_clk)  d_r <= 1'b1;
    end // SLOW_CLOCK
  end // for loop
end // generate
endgenerate
endmodule

I am using Ubuntu 16.04 with Quartus II 17.0

Do you have any idea what could cause the problem with the simulation script? I am still learning how to properly use Quartus II and probably someone with more experience can clearly see what the tool is complaining about.

Thanks in advance for your time :)