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EDing's avatar
EDing
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7 years ago

10AS027E3F29I2SG simulation error

# Time: 0 ps Iteration: 0 Instance: /bsm_epl_pcl_egl_bsf_tst/uut/b2v_inst File: /build/swbuild/SJ/nightly/18.0std/614/l64/work/modelsim/eda/sim_lib/altera_mf.v # ** Error: (vsim-3935) ../../BSM_EP...
MuhammadAr_U_Intel's avatar
MuhammadAr_U_Intel
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7 years ago

Hi Ellen,

I am looking at the log file, it is hard to pin point the exact issue. As I can see a couple of IP's been compiled in the design.

Is it possible to share the design in a private message may be to take a further look ?

Or you can point me what IP was instantiated at line number pointed in Error message.

* Error: (vsim-3935) ../../BSM_EPL_PCL_EGL.vhd(1316): Port 'A_OUT' not found in the connected module.

Also can you confirm if IP is generated in verilog or vhdl ?

Thanks,

Arslan