Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

10500 VHDL syntax error on my counter design.

Hi,

I was wondering if anyone could help me out with solving this error messages.

1 : 10500 VHDL syntax error at coin_reference.vhd(210) near text "then"; expecting ")", or ","

2: 10500 VHDL syntax error at coin_reference.vhd(216) near text "if"; expecting "process".

my counter design is

(line 207) process(G_DOUT(0))

variable count0 : integer range 0 to 65535;

begin

if(rising_edge(G_DOUT(0)) then

if RESET_CLOCK(0) = '1' then

count0 := 0;

elsif enable='1' then

count0 := count0 + 1;

end if;

end if;

Q0 <= count0;

end process;

I honestly don't see what is wrong with it.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    While we're here though, Im a bit concerned you're using a data output as a clock . You should not use logic as clocks. You should only ever use clocks and use the logic as a clock enable.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Yea I've had to change that, the information is only passed to G_DOUT(0) at the very end now, when there is nothing else to perform.