10500 syntax Error

Hey, I'm a beginner and new to VHDL coding.

i was assigned to write code for Simple Moving average Filter with 16 bit ADC by college professor.

since i'm unable to figure out how to interface adc i have written code just for moving average.

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

USE IEEE.std_logic_arith.all;

Entity movavg is

Port(in_ma : IN std_logic_vector(15 DOWNTO 0);

out_ma : OUT std_logic_vector(15 DOWNTO 0););

end movavg;

ARCHITECTURE Behavourial OF movavg IS

signal in_ma : std_logic_vector(15 DOWNTO 0);

signal out_ma : std_logic_vector(15 DOWNTO 0);

inp <= unsigned(in_ma);

x <= to_integer(inp);

for i in 0 to 4195 loop

y(i) <= y(i)+x(i+1);

y_sum <= y/4196 ;

end loop;

y_out <= to_unsigned(y_sum,16);

out_ma <= std_logic_vector(y_out);

end Behavourial;

i'm getting following error

Error (10500): VHDL syntax error at movavg.vhd(13) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable"

Error (10500): VHDL syntax error at movavg.vhd(21) near text "<="; expecting ":", or ","

can someone help me with this ?

also if there are any additional errors please let me know

Thank you.