Altera_Forum
Honored Contributor
9 years ago1-Port ROM only outputting one byte
Hello all,
I used the Mega-Wizard in Quartus to instantiate a single clocked 1-Port ROM block, 64-bit wide, 256 words deep. It's for a Cyclone II FPGA. I created a Memory Initialization File to give it starting values. Here's the beginning of it below: DEPTH = 256; -- The size of memory in words WIDTH = 64; -- The size of data in bits ADDRESS_RADIX = HEX; -- The radix for address values DATA_RADIX = HEX; -- The radix for data values CONTENT -- start of (address : data pairs) BEGIN 0 : 14 21 A1 4B 68 00 CA 9F; 1 : 19 D8 83 23 2B 90 28 4E; I place the 64-bit output into a register, and send it out serially to another device, MSB first. But when I check the serial stream, I see 00s except for the least significant byte. So for Address 0 I see 0000000000000014 stream out, and for Address 1 I see 0000000000000019. I don't see any warnings or errors associated with the memory after compilation. Has anyone seen something like this before?