.sdc for reconfigurable PLL

Hi,

I had never came across such a solution. Then again, I never came across your exact problem. :)

(1) If you're going to change the phase of one of the PLL outputs, I'll point out you'll need to consider that clock asynchronous to the rest. This means dual clock FIFO with 2+ states, etc.

(2) AFAIK, TimeQuest does not support Multi-Mode analysis, which would be the ideal to analyze your solution

Maybe it's possible to emulate it by creating multiple clock constraints at the input clock pin and adding input delays to each clock.

Not sure if this will work.

(3) Personally, this is how I'd do this: implement a solution which can deal with arbitrary input delays and otherwise simply constrain my design for 200 MHz.

Given the data rates involved, I'd go for 4X synchronous oversampling of the input (see Xilinx xapp523 for inspiration).

Another possibility would be to dynamically adjust the phase of the sampling clock produced by the PLL until I can reliably receive data.