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Can you characterize the timing of the input data with respect to the input clock, both as seen at the input pins to the FPGA?
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Here is basic drawing with ideal situation:
https://www.alteraforum.com/forum/attachment.php?attachmentid=13507 Launch CLK - clock from external device
Data delay - time after launch edge data becomes valid (delay is different for different external devices)
Latch CLK - PLL output clock used for latching data.
As you can see from diagram this is DDR interface so both (rising and falling edges are used).
PLL is used to centre align latch clock with data and capture data in the middle of valid window.
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Using a PLL as you propose is probably possible, but it seems like overkill, and reconfiguring a PLL for such a wide locking/tracking range will not be straightforward.
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I am not talking about just one PLL configuration. As I said before I have already implemented PLL with dynamic reconfiguration option and I can change PLL parameters such as M,N,C counter values, phase shift ect. while FPGA is operating. In this case there is no need to have wide PLL lock range. PLL lock range depends on PLL VCO frequency and M,N parameters. If frequency of external device is changed FPGA PLL gets new parameters (M,N,C counter values, phase shift ect.) and PLL reconfiguration is triggered.
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