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Why? Am I trying to solve this problem in some kind of unusual way?
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In a word, yes. It seems to be more complicated than necessary.
Can you characterize the timing of the input data with respect to the input clock, both as seen at the input pins to the FPGA?
If for example the input data changes are referenced to the input clock rising edge then just sampling the input data on either the rising (or falling) edge of the clock might suffice.
Using a PLL as you propose is probably possible, but it seems like overkill, and reconfiguring a PLL for such a wide locking/tracking range will not be straightforward.
You will have to have frequency detection logic, and reprogram the PLL locking parameters based on the detected frequency.
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