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What is the range of the OUTPUT clock of the PLL?
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Same as input 5 - 200MHz.
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That would be the clock to your logic, correct?
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Not only for internal logic. Output clock of PLL is used as a latch clock for input data of external device. Here is basic drawing of my setup :
https://alteraforum.com/forum/attachment.php?attachmentid=13494&stc=1 External device provides clock and data bus for FPGA device. Clock from external device can be changed in range 5-200MHz. Every time when clock from external device has changed FPGA PLL is also reconfigured to work with that frequency (PLL output clock is always the same as input clock) and phase setting is changed to find valid sampling window.
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About the only critical issue (other than meeting timing) will be adding the appropriate input synchronizers to capture the input data reliably.
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That is the reason of this post. I am not concerned in meeting timing in FPGA internal logic , as you said max frequency constrain should be enough to see if it will work. I am interested in checking timing on input pins.
For example:
I have design compiled with my described initial parameters. Input clk to PLL is 200MHz, output clock from PLL is 200MHz, phase shift 0 deg. External device can be replaced with different one (different frequency or in some cases even different data delays on data bus). When different external device is connected I can reconfigure FPGA PLL and change phase to find valid window. Bu how to know from TimeQuest if those two devices will work?
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