.sdc for reconfigurable PLL

What is the range of the OUTPUT clock of the PLL? That would be the clock to your logic, correct? If so, a 'fast' output clock .sdc should probably be sufficient (ie, whatever the highest output clock rate you plan to generate). As long as the FPGA can meet the fastest timing your clock will generate, it will be able to run at a slower rate (basically all the way to DC).

The phase shift on the output clock should not effect the timing of your logic at all.

About the only critical issue (other than meeting timing) will be adding the appropriate input synchronizers to capture the input data reliably.