Altera_Forum
Honored Contributor
Honored Contributor.sdc file: TimeQuest Timing Analyzer (quartus II)
Any good tutorial with examples to setup the .sdc file? Besides, is it possible to generate the Verilog files based on a schematic file (.bdf)?
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Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Any good tutorial with examples to setup the .sdc file? --- Quote End --- timequest user guide (http://www.alterawiki.com/wiki/timequest_user_guide) --- Quote Start --- Besides, is it possible to generate the Verilog files based on a schematic file (.bdf)? --- Quote End --- Yes. In Quartus II: File -> Create / Update -> Create HDL Design File from Current File... Or you can use netlist as tancheeseng84[/b] (http://www.alteraforum.com/forum/member.php?u=73976)[/b] suggested.
