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Altera_Forum
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16 years ago

.BDF/VHDL project with ModelSim

Dear all, My project is composed by a root.bdf file and some vhdl modules. It works correctly in Quartus but I'm not capable to compile it in ModelSim. The problem should be due to the root.vh...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

converting bdf files to VHDL is pretty weak. It assumes all signals are std_logic or std_logic_vector (or in some different cases, it can try and create completly illegal 2d std_logic_vectors). The only way round it is to create root.vhd yourself, rather than auto-generate it from quartus.