Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

.BDF/VHDL project with ModelSim

Dear all, My project is composed by a root.bdf file and some vhdl modules. It works correctly in Quartus but I'm not capable to compile it in ModelSim. The problem should be due to the root.vh...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You should use explicit type conversions in your code. As an example unsigned(vect) to convert a std_logic_vector to unsigned.