XML error when creating a component in SOPC

Hi everyone ,

When creating a new component in SOPC , I got 2 errors :

(1)

Error (10509): Verilog HDL XML interface error at b.v(130): parameter of packed array type is not supported. File: G:/b.v Line: 130

The content of g:/b.v on line 130 is :

130 : parameter [4:0] Reg0 = 5'b00_000, Reg1 = 5'b00_001;

(2)

Error (10670): Verilog HDL or VHDL error: cannot create XML design interface for design file G:/b.v. File: G:/b.v Line: 56

The content of g:/b.v on line 56 is :

56 : module b(

57 : // port declaration

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Have you met these kinds of error before ? What should I do to fix this problem ?

Thanks in advance,

Quan