Wishbone to Avalon Bridge

Giok,

I think so, but you may have to do some VHDL or Verilog work first, to get the signals in a state where they will talk to each other. Once your HDL files have avalon-compliant signals, then yes, use the component editor to bring in all files for that IP core, assign the avalon signals & top-level 'export' signals, and you are good to go.

Sorry, I cannot give a long explanation of how to hook up every wishbone IP core to Avalon. However, I really do reccomend that anyone interested study the various examples that people have provided -- There is the opencores ethernet MAC, which shows both master and slave ports, and the I2C core, posted in the 'post your own IP' section of this forum. When I worked with the MAC core I documented the verilog where ever a change was required to explain the conversion between wishbone and avalon. I have not studied the I2C peripheral but perhaps it is the same (actually a few years ago I hooked up the i2c core to avalon with -no- exrta logic required.. however they may have changed things since then).

Edit: to Giok and wdzwdx -- I just had a look at the 'post your ip' section and the I2C example should illustrate simple avalon master --> wishbone slaves well. There is also the CAN controller which is a bit more complex.