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Honored Contributor
Honored ContributorWhy my Nios II run slowly ?
Dear all, I have do experiment on the Cyclone V SOC. [Helio evaluation board] And I put one nios/e and onchip-ram into the FPGA fabric. Currently, I could read/write the data in...
Altera_ForumHonored Contributor
Honored Contributor>> All components[including NiosII] are connected to clk and it is default for 50Mhz.
Ok, good. Another thing to try is to instrument Nios with SignalTap and see what instructions it executes in that slow line of code. See the following document, page 17: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an446.pdf
